2007 Final Exam

Date: Dec. 6, 2007

1. [30-points] Each statement below contains an argument on the model of computation. If you agree on the argument, explain the reason why it is so. Otherwise, explain why it is not.

[1-1] [10-points] Discrete-event model is inappropriate for initial specification from which the system is refined to implementation, even though it is the default model of SystemC.

[1-2] [10-points] Synchronous-reactive model is a good specification model for hardware implementation, but not for software implementation.

[1-3] [10-points] UML-based specification for embedded SW is becoming more popular. The current UML specification can be successfully used for MPSoC design.

2. [15-points] Answer the following questions regarding on the Kahn Process Networks (KPN).

[2-1] [5-points] KPNs are known to be "deterministic". What does it mean and why is it important?

[2-2] [10-points] There are two execution policies for a KPN: demand driven and data driven. Compare these approaches and show simple examples to show that one is better than the other.

3. [15-points] A system consists of two concurrent FSM machines: One FSM produces an output (u=1) when the number of "1"s received so far becomes odd. The other FSM toggles its output value (v) between 0 and 1 each time (u=1) is produced.

For example:

input = 0  0  1  0  0  1  1  1  0  1

u = 0  0  1  0  0  0  1  0  0  1

v = 0  0  1  1  1  1  0  0  0  1

[3-1] [10-points] Draw a concurrent FSM specification for the system

[3-2] [5-points] Translate the specification to a flat FSM that has the minimum number of states.

4. [10-points] Below is a simplified SIMULINK specification. What will be printed at the output during time period [0, 20]

5. [10-points] Giotto and TM (Timed-Multitasking) models are both proposed for models of embedded SW design. Discuss their similarities and differences briefly.

6. [10-points] In the Y-chart approach of design space exploration, we need to prepare block-performance information of each block on a each processing element for mapping behavior specification onto the target architecture. What factors should we consider to estimate the software performance?

7. [15-points] From the SDF specification as shown below, we'd like to synthesize the HW automatically. The number in a parenthesis indicates the execution cycle of node execution. Assume that node A can be executed in parallel, but C should be executed sequentially since it has an internal state.

Answer the following questions

[7-1] [10-points] There are three different ways of refinement as follow:

- GRAPE's approach: distributed control

- Meyer's approach: centralized control with static timing

- Ptolemy's approach: fully parallel implementation

Draw a simplified structure of the generated hardware from each approach.

[7-2] [5-points] In PeaCE approach, we can parallelize node A partially. If we parallelize two invocations of node A, draw the structure of the generated hardware.

“And let us now grow weary while doing good, for in due season we shall reap if we do not lose heart"  (Galatian 6:9)

2007 Midterm Exam

Date: Nov. 8, 2007

1. [25-points] Answer the following questions briefly.

[1-1] [10-points] PICO Express is a C-based design tool. What are the benefits of using these tools for hardware design compared with HDL-based design?

[1-2] [5-points] Define the HW/SW codesign methodology in a single sentence that explains the main difference from the conventional design methodology.

[1-3] [10-points] Suppose you want to design a hardware IP for business purpose. Besides the functionality of the IP, explain what issues you have to consider?

2. [30-points] The basic method of synchronizing component simulators in a timed HW/SW cosimulation environment is lock-step synchronization where all simulators are synchronized every cycle. The HW/SW cosimulation time based on lock-step synchronization can be formulated as follows:

(1)

: total simulated cycles

: number of component simulators

: simulation time to advance one cycle of simulator i.

synchronization overhead paid by simulator i

: simulation time to perform data transaction between simulators. In a shared memory system, it represents the sum of bus access time and memory access time.

: the total number of communication transactions during simulation.

Answer the following questions.

[2-1] [10-points] It is claimed that a cycle-accurate TLM simulator (SoC Designer of ARM) is more than 100 times faster than a RTL simulator (Seamless CVE). Explain where this speed-up comes from (in equation (1)).

[2-2] [5-points] Recently, cycle-approximate TLM simulator achieves more than 100 times faster than the cycle-accurate TLM simulator. Explain where this speed-up comes from.

[2-3] [10-points] Equation (1) was obtained based on the assumption that a single host machine runs all component simulators. Modify the equation for parallel cosimulation where component simulators are distributed to dedicated machines. Make sure that one simulator is for communication architecture and the simulator should wait until all requests from processing components are arrived.

[2-4] [5-points] In case we use virtual synchronization technique, explain how equation (1) can be modified. Explain how we can get speed-up with virtual synchronization technique.

3. [30-points] Answer the following questions on the dataflow graph shown below.

[3-1] [5-points] Compute y to make a sample-rate consistent graph. And find the repetition counts of nodes in a single iteration: [eqn: r _{A} ,`r _{B,} `r _{C,``} r _{D}]

[3-2] [10-points] Find a single-appearance schedule of the graph and compute the total buffer requirement with and without buffer sharing respectively.

[3-3] [5-points] Find a schedule that has the minimum buffer requirement.

[3-4] [10-points] Show how we can change the nodes B and D to make the graph as a CSDF that has the same behavior but with smaller buffer sizes.

4 [15 points] Answer the following questions regarding SystemC language.

[4-1] [10 points] SystemC supports three types of processes. Suppose that we want to design a system that consists of four blocks as shown in the right side. Explain what types of processes are you going to use to model the blocks and why.

[4-2] [5 points] What is the difference between sc_signal and sc_buffer channels? On the channel between block A and B in the above figure, what channel are you going to use and why?

5. [10-points] More and more processing components are integrated in a single chip. Among four main issues of HW/SW codesign (modeling, DSE, simulation, and synthesis), explain your opinion which one is likely to be most difficult and why.

“And God said, "Let there be light" and there was light."  (Genesis 1:3)