Digital Logic Design and Lab

coursetab

c_weekno	Title	Body
Lab 1	Measurement techniques, Understanding logic gates
Lab 10	Term project
Lab 10	Term project (continued)
Lab 2	Boolean algebra, Logic minimization
Lab 3	K-map, multi-level/multi-output logic
Lab 4	PLD, Steering logic
Lab 5	Latch/flip-flop
Lab 6	Memory, Seven-segment display control
Lab 7	Counter, Register
Lab 8	FSM
Lab 9	Traffic light controller
W01	Introduction (Chap. 1), Boolean algebra (Chap. 2)
W02	Logic gates, Boolean expression (Chap. 2)
W03	Karnaugh map method (Chap. 2)
W04	Quine-McClusky method, Espresso, Multi-level logic (Chap. 3)
W05	AOI/OAI gates, Gate delay, HDL (Chap. 3)
W06	Fixed logic, ROM, Steering logic (Chap. 4)
W07	PLD, Two-level/multi-level logic, Non-gate logic (Chap. 4)
W08	Midterm exam., Combinational logic design examples (Chap. 5)
W09	Sequential logic, Memories (Chap. 6, Chap. 10)
W10	FSM (Chap. 7)
W11	FSM optimization (Chap.8)
W12	Sequential logic implementation (Chap. 9)
W13	Sequential logic examples, Number system (Chap. 10, App. A)
W14	Arithmetic circuits (Chap. 5)
W15	Final exam.

code:

420.201A_2007F

level:

year:

term:

staff:

Prof. Chae, Soo Ik

c_regdate:

2008-09-06 10:04:25

department: